1. Field of the Invention
The present invention relates to a semiconductor memory device. More specifically, the invention relates to a semiconductor memory device having a 5-transistor SRAM (static random access memory) cell structure.
2. Description of the Related Art
Recently, in 6-transistor SRAM cells, it has been more difficult to ensure stability as variations in threshold value increase due to microfabrication of transistors. In contrast, 5-transistor SRAM cells are so configured that the sizes and threshold values of transistors making up the cells become asymmetrical and thus have an advantage that its stability is secured more easily than the 6-transistor SRAM cells without increasing the cell size or reducing the cell current. A 6-transistor SRAM cell tends to be configured so as to read data through a single port; therefore, a difference in access speed between the prior art 5-transistor SRAM cell (having a dual port) and the 6-transistor SRAM cell becomes smaller, though the 5-transistor SRAM cell had a great disadvantage in access speed. In the prior art 5-transistor SRAM cells, however, it is difficult to write data “1” while keeping data of non-selected cells, and thus the cells are difficult to achieve as an array.
The structure of a prior art 5-transistor SRAM cell will now be described in brief. As shown in FIG. 10, the prior art 5-transistor SRAM cell includes a pair of CMOS (complementary metal oxide semiconductor) inverter circuits 101 and 102 each having a latch structure for data storage and an input/output control transistor (gate transistor) 103 which is connected between the output terminal of the CMOS inverter circuit 101 and a bit line BL and whose gate is connected to a word line WL. The 5-transistor SRAM cell can reduce the number of transistors and that of bit lines by one and thus its area reduction effect is greater than that of the 6-transistor SRAM cell.
The prior art 5-transistor SRAM cell has only one bit line BL. Therefore, the same bit line BL has to be used to write both data “0” and “1.”
An operation of writing data “1” in the prior art 5-transistor SRAM cell will now be described. In “1” data write mode, the bit line BL is set at a high (Hi) level to turn on a gate transistor 103 as shown in FIG. 11. If, in this time, the output (Lo→Hi) of the CMOS inverter circuit 101 becomes higher than the threshold value of input of the CMOS inverter circuit 102, the output of the CMOS inverter circuit 102 is inverted (Hi→Lo). Accordingly, the input of the CMOS inverter circuit 101 is inverted and thus writing of data “1” is completed.
The output of the CMOS inverter 101 in “1” data write mode depends upon the ratio of on-resistance of the gate transistor 103 to that of a driver transistor (N-type MOS transistor) 101a. It is thus necessary to set the above on-resistance such that the output of the CMOS inverter circuit 101 becomes considerably greater than the threshold value of the input of the CMOS inverter circuit 102. In most cases, however, the on-resistance of the driver transistor 101a has to be set lower in order to ensure the cell current and stabilize the cell. For this reason, conventionally, it was difficult to set the above on-resistance such that the output of the CMOS inverter circuit 101 became very high in “1” data write mode.